LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   C:\Program Files\Labcenter Electronics\3RD PARTY LIBS_MODELS\VSM.LIBS SAMPLES\CMOS SERIES MODEL DESIGNS\4521\4521.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  06/08/03
Modified: 06/08/03

*PROPERTIES,1    
TGQ=?

*MAPPINGS,3,VALUE+VOLTAGE
4521+5V : TDLHDQ=140n, TDHLDQ= 140n , TDCQ= 6u, TDRQ= 100n, TGQ=?
4521+10V : TDLHDQ=55n, TDHLDQ=55n , TDCQ= 2.2u, TDRQ= 50n,TGQ=?
4521+15V : TDLHDQ= 40n, TDHLDQ=40n,  TDCQ= 1.7u, TDRQ= 40n,TGQ=?

*MODELDEFS,0    

*PARTLIST,11   
U1,TRIBUFFER,TRIBUFFER,PRIMITIVE=DIGITAL
U2,INVERTER,INVERTER,PRIMITIVE=DIGITAL,TDHLDQ=<TDHLDQ>,TDLHDQ=<TDLHDQ>,TGQ=<TGQ>
U3,DIVIDER,DIVIDER,PRIMITIVE=DIGITAL,RATIO=8,TDCQ=<TDCQ>,TDRQ=<TDRQ>,TGQ=<TGQ>
U4,DIVIDER,DIVIDER,PRIMITIVE=DIGITAL,RATIO=8,TDCQ=<TDCQ>,TDRQ=<TDRQ>,TGQ=<TGQ>
U5,DIVIDER,DIVIDER,PRIMITIVE=DIGITAL,RATIO=2,TDCQ=<TDCQ>,TDRQ=<TDRQ>,TGQ=<TGQ>
U6,DIVIDER,DIVIDER,PRIMITIVE=DIGITAL,RATIO=2,TDCQ=<TDCQ>,TDRQ=<TDRQ>,TGQ=<TGQ>
U7,DIVIDER,DIVIDER,PRIMITIVE=DIGITAL,RATIO=2,TDCQ=<TDCQ>,TDRQ=<TDRQ>,TGQ=<TGQ>
U8,DIVIDER,DIVIDER,PRIMITIVE=DIGITAL,RATIO=2,TDCQ=<TDCQ>,TDRQ=<TDRQ>,TGQ=<TGQ>
U9,DIVIDER,DIVIDER,PRIMITIVE=DIGITAL,RATIO=2,TDCQ=<TDCQ>,TDRQ=<TDRQ>,TGQ=<TGQ>
U10,DIVIDER,DIVIDER,PRIMITIVE=DIGITAL,RATIO=2,TDCQ=<TDCQ>,TDRQ=<TDRQ>,TGQ=<TGQ>
U11,DIVIDER,DIVIDER,PRIMITIVE=DIGITAL,RATIO=2,TDCQ=<TDCQ>,TDRQ=<TDRQ>,TGQ=<TGQ>

*NETLIST,13   
#00000,2
U3,IP,CLK
U4,OP,Q

#00001,2
U3,OP,Q
U5,IP,CLK

OUT2,5
OUT2,OT
IN2,IT
U2,IP,D
U2,OP,Q
U4,IP,CLK

IN1,2
IN1,IT
U1,IP,D

OUT1,2
OUT1,OT
U1,TS,Q

RST,11
RST,IT
U1,IP,OE
U4,IP,RST
U3,IP,RST
U9,IP,RST
U11,IP,RST
U10,IP,RST
U5,IP,RST
U8,IP,RST
U7,IP,RST
U6,IP,RST

Q18,3
Q18,OT
U6,IP,CLK
U5,OP,Q

Q19,3
Q19,OT
U7,IP,CLK
U6,OP,Q

Q20,3
Q20,OT
U8,IP,CLK
U7,OP,Q

Q21,3
Q21,OT
U9,IP,CLK
U8,OP,Q

Q22,3
Q22,OT
U10,IP,CLK
U9,OP,Q

Q23,3
Q23,OT
U11,IP,CLK
U10,OP,Q

Q24,2
Q24,OT
U11,OP,Q

*GATES,0    

