LISA MODEL DESCRIPTION FORMAT 6.1
=================================
Design:   K:\PROLIBS\MCS8051\AT89CX051\AT89CX051.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  19/07/03
Modified: 12/09/06

*PROPERTIES,10   
TRACE_CORE=1
TRACE_EEPROM=1
TRACE_INTERRUPT=1
TRACE_LOAD=1
TRACE_SETUP=1
TRACE_TIMER0=1
TRACE_TIMER1=1
TRACE_TIMER2=1
TRACE_USART=1
TRACE_WDT=1

*MAPPINGS,2,COMPARATOR
0 : OPT="1,2", NOPT=[NULL]
1 : OPT=[NULL], NOPT="1,2"

*MAPPINGS,3,VALUE
AT89C1051 : ROM=1024, IRAM=64
AT89C2051 : ROM=2048, IRAM=128
AT89C4051 : ROM=4096, IRAM=128

*MODELDEFS,1    
89CX051ITF : RHI=50,RLO=50,V+=VCC,V-=GND

*PARTLIST,5    
AD1,ADC,ADC,PRIMITIVE=ANALOG,RNEG=100M,RPOS=100M,TTOL=1u,V+=VCC,V-=GND,VHH=0.5,VHL=0.5,VTH=3.5,VTL=1.5
E1,VCVS,1E6,PRIMITIVE=ANALOGUE
R1,RESISTOR,,CONNECT=<OPT>,PRIMITIVE=NULL
R2,RESISTOR,,CONNECT=<OPT>,PRIMITIVE=NULL
U1,80C51_CORE,80C51_CORE,CLOCK=<CLOCK>,DBG_FETCH=0,EEPROM=0,HWDOG=0,IRAM=<IRAM>,MFR=ATMEL,MODDLL=<MODDLL>,PRIMITIVE=DIGITAL,PROGRAM=<PROGRAM>,ROM=<ROM>,TRACE_CORE=<TRACE_CORE>,TRACE_EEPROM=<TRACE_EEPROM>,TRACE_INTERRUPT=<TRACE_INTERRUPT>,TRACE_LOAD=<TRACE_LOAD>,TRACE_SETUP=<TRACE_SETUP>,TRACE_TIMER0=<TRACE_TIMER0>,TRACE_TIMER1=<TRACE_TIMER1>,TRACE_TIMER2=<TRACE_TIMER2>,TRACE_USART=<TRACE_USART>,TRACE_WDT=<TRACE_WDT>,X2=0,XRAM=0

*NETLIST,43   
#00000,1
U1,OP,ALE

#00001,1
U1,IP,$EA$

#00002,1
U1,OP,$PSEN$

#00003,1
U1,IO,P0.0/AD0

#00004,1
U1,IO,P0.1/AD1

#00005,1
U1,IO,P0.2/AD2

#00006,1
U1,IO,P0.3/AD3

#00007,1
U1,IO,P0.4/AD4

#00008,1
U1,IO,P0.5/AD5

#00009,1
U1,IO,P0.6/AD6

#00010,1
U1,IO,P0.7/AD7

#00011,1
U1,IO,P2.7/A15

#00012,1
U1,IO,P2.0/A8

#00013,1
U1,IO,P2.1/A9

#00014,1
U1,IO,P2.2/A10

#00015,1
U1,IO,P2.3/A11

#00016,1
U1,IO,P2.4/A12

#00017,1
U1,IO,P2.5/A13

#00018,1
U1,IO,P2.6/A14

#00019,2
U1,IO,P1.0
R2,PS,2

#00020,2
U1,IO,P1.1
R1,PS,2

#00021,2
U1,IP,P3.6/$WR$
AD1,PS,D

#00022,2
AD1,PS,A
E1,PS,+

XTAL2,2
XTAL2,GT
U1,OP,XTAL2

XTAL1,2
XTAL1,GT
U1,IP,XTAL1

RST,2
RST,GT
U1,IP,RST

P3.0/RXD,2
P3.0/RXD,GT
U1,IO,P3.0/RXD

P3.1/TXD,2
P3.1/TXD,GT
U1,IO,P3.1/TXD

P3.2/$INT0$,2
P3.2/$INT0$,GT
U1,IO,P3.2/$INT0$

P3.3/$INT1$,2
P3.3/$INT1$,GT
U1,IO,P3.3/$INT1$

P3.4/T0,2
P3.4/T0,GT
U1,IO,P3.4/T0

P3.7,2
P3.7,GT
U1,IO,P3.7/$RD$

P3.5/T1,2
P3.5/T1,GT
U1,IO,P3.5/T1

VCC,3
VCC,PT
AD1,PP,V+
U1,PP,VCC

GND,4
GND,PT
E1,PS,-
AD1,PP,V-
U1,PP,GND

P1.0,3
P1.0,GT
E1,PS,P
R2,PS,1

P1.1,3
P1.1,GT
E1,PS,N
R1,PS,1

P1.2,2
P1.2,GT
U1,IO,P1.2

P1.3,2
P1.3,GT
U1,IO,P1.3

P1.4,2
P1.4,GT
U1,IO,P1.4

P1.5,2
P1.5,GT
U1,IO,P1.5

P1.6,2
P1.6,GT
U1,IO,P1.6

P1.7,2
P1.7,GT
U1,IO,P1.7

*GATES,0    

