LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   C:\Program Files\Labcenter Electronics\VSM.LIBS\VSM.LIBS SAMPLES\DIGITAL POTS\DIGITAL POTS models designs\ADRDAC PARTS  SCRATCH FOLDER\ADLTCHRDAC.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  14/02/04
Modified: 01/04/04

*PROPERTIES,1    
POTVAL=<POTVAL>

*MODELDEFS,1    
ITFRDC : V+=VCC,V-=DGND,FLOAT=HIGH

*PARTLIST,17   
AVS1,AVS,"1.0*V(A,B)",PRIMITIVE=ANALOGUE
AVS2,AVS,"5-V(A,B)",PRIMITIVE=ANALOGUE
DAC1,DAC_8,DAC_8,MODDLL=DATAC,MODE=UNSIGNED,PRIMITIVE=PASSIVE,SLEWRATE=1E6,TDDA=0
G402D8499,VDC!,5,HIDDENPROPS=TRUE,MANUALEDITS=FALSE,PRIMITIVE=PROBE
M402D8499,VPROBE,DAC1(VREF+),PRIMITIVE=PROBE
R1,RESISTOR,10k,PRIMITIVE=ANALOGUE
R2,RESISTOR,1T,PRIMITIVE=ANALOGUE
R3,RESISTOR,1T,PRIMITIVE=ANALOGUE
R4,RESISTOR,1T,PRIMITIVE=ANALOGUE
S1,VCR,VCR,PRIMITIVE=ANALOGUE,ROFF=<POTVAL>,RON=1u,VOFF=0,VON=5
S2,VCR,VCR,PRIMITIVE=ANALOGUE,ROFF=<POTVAL>,RON=1u,VOFF=0,VON=5
SW1,DSWITCH,DSWITCH,PRIMITIVE=PASSIVE,ROFF=100M,RON=1,TSWITCH=1u
SW2,DSWITCH,DSWITCH,PRIMITIVE=PASSIVE,ROFF=100M,RON=1,TSWITCH=1u
SW3,DSWITCH,DSWITCH,PRIMITIVE=PASSIVE,ROFF=100M,RON=1,TSWITCH=1u
SW4,DSWITCH,DSWITCH,PRIMITIVE=PASSIVE,ROFF=100m,RON=100M,TSWITCH=1u
U1,LATCH_8,LATCH_8,EDGE=0,INIT=128,INVERT=RESET,PRIMITIVE=DIGITAL
U2,OR_2,OR_2,PRIMITIVE=DIGITAL

*NETLIST,33   
#00000,4
DAC1,PS,VOUT
AVS1,PS,A
AVS2,PS,A
R1,PS,2

#00001,3
DAC1,PS,VREF+
G402D8499,OP,*
M402D8499,IP,*

#00002,2
DAC1,IP,LE
U2,OP,Q

#00003,2
DAC1,IP,D0
U1,OP,Q0

#00004,2
DAC1,IP,D1
U1,OP,Q1

#00005,2
DAC1,IP,D2
U1,OP,Q2

#00006,2
DAC1,IP,D3
U1,OP,Q3

#00007,2
DAC1,IP,D4
U1,OP,Q4

#00008,2
DAC1,IP,D5
U1,OP,Q5

#00009,2
DAC1,IP,D6
U1,OP,Q6

#00010,2
DAC1,IP,D7
U1,OP,Q7

#00011,2
S1,PS,+
SW3,IO,A

#00012,3
S1,PS,-
SW1,IO,A
S2,PS,-

#00013,2
S1,PS,P
AVS1,PS,+

#00014,2
S2,PS,+
SW2,IO,A

#00015,2
S2,PS,P
AVS2,PS,+

GND,9
GND,PR
DAC1,PS,VREF-
AVS1,PS,B
AVS1,PS,-
AVS2,PS,-
S1,PS,N
S2,PS,N
AVS2,PS,B
R1,PS,1

AGND,4
AGND,GT
R2,PS,1
R3,PS,1
R4,PS,1

B,4
B,GT
R2,PS,2
SW4,IO,B
SW2,IO,B

W,4
W,GT
R3,PS,2
SW4,IO,A
SW1,IO,B

A,3
A,GT
R4,PS,2
SW3,IO,B

$SHDN$,5
$SHDN$,IT
SW1,IP,EN
SW3,IP,EN
SW2,IP,EN
SW4,IP,EN

D0,2
D0,IT
U1,IP,D0

D1,2
D1,IT
U1,IP,D1

D2,2
D2,IT
U1,IP,D2

D3,2
D3,IT
U1,IP,D3

D4,2
D4,IT
U1,IP,D4

D5,2
D5,IT
U1,IP,D5

D6,2
D6,IT
U1,IP,D6

D7,2
D7,IT
U1,IP,D7

RDAC,4
RDAC,IT
U1,IP,CLK
U2,IP,D0
U1,IP,EN

$RS$,3
$RS$,IT
U1,PS,RESET
U2,IP,D1

VCC,2
VCC,PR
U1,IP,OE

*GATES,0    

