LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   C:\Program Files\Labcenter Electronics\VSM.LIBS\VSM.LIBS SAMPLES\DIGITAL POTS\DIGITAL POTS models designs\ADRDAC PARTS\ADSDO.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  12/02/04
Modified: 14/02/04

*PROPERTIES,0    

*MODELDEFS,1    
ITFADRDSDO : RHI=5,RLO=5, V+=VDD,V-=DGND

*PARTLIST,5    
U1,DTFF,DTFF,INVERT=RESET,PRIMITIVE=DIGITAL
U2,AND_3,AND_3,PRIMITIVE=DIGITAL
U3,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U4,INVERTER,INVERTER,PRIMITIVE=DIGITAL
U5,INVERTER,INVERTER,PRIMITIVE=DIGITAL

*NETLIST,12   
#00000,2
U1,IP,CLK
U5,OP,Q

#00001,2
U1,OP,Q
U3,IP,D

#00002,1
U1,OP,!Q

#00003,2
U2,IP,D1
U4,OP,Q

#00004,2
U2,IP,D2
U3,OP,Q

SDI,2
SDI,IT
U1,IP,D

$RS$,2
$RS$,IT
U1,IP,RESET

DGND,2
DGND,PR
U1,IP,SET

$SHDN$,2
$SHDN$,IT
U2,IP,D0

SDO,2
SDO,OT
U2,OP,Q

$CS$,2
$CS$,IT
U4,IP,D

CLK,2
CLK,IT
U5,IP,D

*GATES,0    

