LISA MODEL DESCRIPTION FORMAT 6.0
=================================
Design:   C:\Program Files\Labcenter Electronics\VSM.LIBS\VSM.LIBS SAMPLES\CMOS SERIES MODEL DESIGNS\4043\4043.DSN
Doc. no.: <NONE>
Revision: <NONE>
Author:   <NONE>
Created:  02/02/02
Modified: 06/06/04

*PROPERTIES,1    
TGQ=?

*MAPPINGS,6,VALUE+VOLTAGE
4043+5V : TDSQ= 175n, TDRQ=175n, TGQ=?
4043+10V : TDSQ= 75n,   TDRQ=75n,   TGQ=?
4043+15V : TDSQ= 60n,   TDRQ=60n,   TGQ=?
CD4043+5V : TDSQ= 175n, TDRQ=175n, TGQ=?
CD4043+10V : TDSQ= 75n,   TDRQ=75n,   TGQ=?
CD4043+15V : TDSQ= 60n,   TDRQ=60n,   TGQ=?

*MODELDEFS,0    

*PARTLIST,8    
U1,TRIBUFFER,TRIBUFFER,PRIMITIVE=DIGITAL
U2,TRIBUFFER,TRIBUFFER,PRIMITIVE=DIGITAL
U3,TRIBUFFER,TRIBUFFER,PRIMITIVE=DIGITAL
U4,TRIBUFFER,TRIBUFFER,PRIMITIVE=DIGITAL
U5,JKFF,JKFF,PRIMITIVE=DIGITAL,TDRQ=<TDRQ>,TDSQ=<TDSQ>,TGQ=<TGQ>
U6,JKFF,JKFF,PRIMITIVE=DIGITAL,TDRQ=<TDRQ>,TDSQ=<TDSQ>,TGQ=<TGQ>
U7,JKFF,JKFF,PRIMITIVE=DIGITAL,TDRQ=<TDRQ>,TDSQ=<TDSQ>,TGQ=<TGQ>
U8,JKFF,JKFF,PRIMITIVE=DIGITAL,TDRQ=<TDRQ>,TDSQ=<TDSQ>,TGQ=<TGQ>

*NETLIST,33   
#00000,2
U1,IP,D
U5,OP,Q

#00001,2
U2,IP,D
U6,OP,Q

#00002,2
U3,IP,D
U7,OP,Q

#00003,2
U4,IP,D
U8,OP,Q

#00004,1
U5,IP,CLK

#00005,1
U5,OP,!Q

#00006,1
U5,PS,J

#00007,1
U5,PS,K

#00008,1
U6,IP,CLK

#00009,1
U6,OP,!Q

#00010,1
U6,PS,J

#00011,1
U6,PS,K

#00012,1
U7,IP,CLK

#00013,1
U7,OP,!Q

#00014,1
U7,PS,J

#00015,1
U7,PS,K

#00016,1
U8,IP,CLK

#00017,1
U8,OP,!Q

#00018,1
U8,PS,J

#00019,1
U8,PS,K

Q0,2
Q0,OT
U1,TS,Q

E,5
E,IT
U1,IP,OE
U4,IP,OE
U3,IP,OE
U2,IP,OE

Q1,2
Q1,OT
U2,TS,Q

Q2,2
Q2,OT
U3,TS,Q

Q3,2
Q3,OT
U4,TS,Q

R0,2
R0,IT
U5,IP,RESET

S0,2
S0,IT
U5,IP,SET

R1,2
R1,IT
U6,IP,RESET

S1,2
S1,IT
U6,IP,SET

R2,2
R2,IT
U7,IP,RESET

S2,2
S2,IT
U7,IP,SET

R3,2
R3,IT
U8,IP,RESET

S3,2
S3,IT
U8,IP,SET

*GATES,0    

